GDC21D003 Datasheet, PDF (56/77 Pages) Hynix Semiconductor – VSB Receiver

I
(input)
GDC21D003
Gain
X
Accumulator
Limiter
Delay
Offset
+ ^I’
Hilbert
Q’
Transform
Filter
Accumulator
Limiter
I
I”
(output)
Derotator
Q”
Error Decision
cos sine
Sine
Cosine
Table
Accumulator
Limiter
Phase
Error
Slice Prediction
from
Viterbi Decoder
Gain Error
Offset Error
Figure 6.5.1 Phase Tracker
6.5.1 Error Detection
The result I signal is output to channel decoder and
used at error detection with result Q signal to get
estimated phase error degree. Figure 6.5.2 shows
the block diagram of error detection. Result
I signal is input to VSB mapper which is a Look-up
table and the output of this look-up table is a kind
of decision error. The 2^nd Look-up Table converts
decision error to gain error, offset error, and phase
error. And these error information are accumulated
and used to remove phase noise.
VSB mode
I”
2VSB mapper
Gain Error
4VSB mapper
8VSB mapper
MUX
Error
Lookup
Table
Offset Error
Phase Error
16VSB mapper
Q”
Figure 6.5.2 Error Detection
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