GDC21D003 Datasheet, PDF (61/77 Pages) Hynix Semiconductor – VSB Receiver

GDC21D003
Comb Filter
Segment Sync Removal
¢²
Equalizer
£-
Phase Tracker
D
¢²
D
M to
U
X
Viterbi
Decoder
VSB Synchonizer/Equalizer
(D = 12 Symbols Delay)
Figure 6.6.3 Segment Sync Suspension
6.6.3 Viterbi Decoder
The Viterbi decoder performs the task of slicing
and convolutional decoding. It has two modes; one
is for the case when the NTSC rejection filter is
used to minimize NTSC co-channel, and the other
is when it is not used. This is illustrated in Figure
6.6.4. The insertion of the NTSC rejection filter is
determined automatically in the comb filter control
block(before the equalizer, see Figure 6.6.3), with
this information passed to the Viterbi decoder .
When there is little or no NTSC co-channel
interference, the NTSC rejection filter is not used
and an optimal Viterbi decoder is used to decode
the 4-state trellis-encoded data. Serial bits are re-
created in the same order as they were created in
the encoder. With significant NTSC co-channel
interference, if the NTSC rejection filter(12 symbol,
feed-forward subtractive comb) is employed, an
optimized 8-state Viterbi decoder for this partial
response channel is used. The Viterbi decoder can
be bypassed for performance tests by setting I²C
register64[5](Viterbi_on) to ‘0’. Then, just 4-level
slicing is done. Also, on ATSC 16 VSB and
MMDS 2/4/8/16 VSB mode, the Viterbi decoder is
bypassed and only slicing is done. Figure 6.6.5 is
internal block diagram of Viterbi decoder. Each
branch metric of trellis calculated in branch metric
block is 6bits, memory depth of path memory
block is 16. Branch metric block and ACS(Add,
Compare, and Select) block are adapted to be 4-
state Viterbi decoder if I²C register84[4](Ncomb)
value is ‘1’, or 8-state Viterbi decoder if it is ‘0’.
12 Vitervi decoders are implemented through 12
shift registers sharing one Branch metric block and
one ACS block.
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