GDC21D003 Datasheet, PDF (16/77 Pages) Hynix Semiconductor – VSB Receiver

5. I²C Bus I/F & Registers
5.1 I²C Bus I/F Description
When NI²CEN pin is set to Low, the GDC21D003
may be controlled over I²C bus interface which
consists of two signals, serial data(SDA) and serial
clock(SCL) that can control a large number of
devices on a common bus. The Device Address of
this chip is “1011001”b or “0001110”b which can
be selected by I²CSEL pin. The data on the I²C bus
can be transferred at a rate up to 100 kbits/s in the
standard mode, or up to 400 kbits/s in the fast
mode. In the GDC21D003, SDA is bi-directional
but SCL is only used as input, since the IC can only
act as a slave device. In normal operations, data
transfers are clocked by the SCL signal with one
SCL pulse per data bit, and SDA is required to be
stable during the high period of the SCL signal.
Transitions of SDA while SCL is high are
performed by the interface signals of start(S),
stop(P), and repeated start(Sr) conditions. The start
condition is defined as a high-to-low transition of
SDA while SCL is high, and the stop condition is
the low-to-high transition of SDA while SCL is
high. Data transmissions are always proceeded by a
start condition and ended with a stop condition, and
may contain repeated starts within the transmission
to alter the direction of the data flow or to change
register base addresses. All data transmission
GDC21D003
operations occur in 8-bit blocks with each block
acknowledged through the designated receiver by
the generation of an acknowledge signal(A). This
signal is generated on the ninth pulse of SCL for
each transferred block.
5.1.1 Write Operation
In order to perform a write operation, the interface
is accessed in following manner. The master first
generates a start condition by pulling SDA down to
low while SCL is high. The master next sends a 7-
bit Device Address and a one bit R/W signal, and
each slave compares this address with its own
address and acknowledges the master if the device
address sent by the master coincides with that of its
own. If not so, the slave ignores the rest of current
data being transmitted. If the master is writing to
the GDC21D003, the chip interprets the next data
byte as a register base address. This is used as the
location to store the next received data byte. This
base address increases as each data byte is received
allowing a contiguous register block to be
programmed in a single transmission. Non-
contiguous blocks may be programmed in multiple
transmissions or by using a repeated start condition,
which allows a new Device Address and register
base address to be specified without the master
giving up control of the bus. The transmission is
terminated with the receipt of a stop condition.
SDA S DEV. ADDRESS W A BASE ADDRESS A
DATA #1 A … DATA #N
AP
ISSUED BY MASTER
ISSUED BY GDC21D003
Figure 5.1.1 I²C Write Operation Example
5.1.2 Read Operation
Read operation is performed in a manner similar
to write operation. The master first generates a
start condition and then sends the Device Address
and R/W signal. The master will acknowledge
each byte as receiving if it desires another byte to
be sent. At the end of the transmission, the master
will not acknowledge the slave and will then be
free to generate a stop condition to terminate the
transmission. The base address register contents
are used to determine the location to be read, and
once again this address will be increased with each
successive read. Because the base address register
can only be programmed through a write operation,
a general read will require two accesses or a single
access with a embedded repeated start to change
the direction of transmission.
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