GDC21D003 Datasheet, PDF (40/77 Pages) Hynix Semiconductor – VSB Receiver

GDC21D003
DC Reduction
10
10
10
Polarity Inverse
Multiplexer
Polarity Correction
polarity
Fig 6.3.7 The Block Diagram of Polarity Correction
Figure 6.3.7 is Polarity Correction block diagram.
Output signal polarity is corrected by control of
polarity from Polarity Decision block.
6.3.5 Data Segment Sync Recovery
At DTV transmitter part Data Segment Sync is
inserted for 4-symbol period in every Data
Segment. This Data Segment Sync has (1,0,0,1)
pattern.
DTV receiver compares inputted signal pattern
with Data Segment Sync pattern (1, 0, 0, 1)
inputted from transmitter and acknowledges the
most similar pattern as Data Segment Sync interval.
But because the inputted signal at the beginning of
activation has polarity ambiguity generated by
FPLL, inverted polarity pattern of Data Segment
Sync (1, 0, 0, 1) from transmitter is acknowledged
as Data Segment Sync interval. After completion of
initial Data Segment Sync detection, input signal
polarity is detected from Polarity Decision block at
the end. Also after polarity correction in Polarity
Correction block, only positive polarity is
acknowledged as Data Segment Sync interval. And
Data Segment Sync detection becomes easier under
close Ghost environment by improving its
performance. Figure 6.3.8 shows the improved
Data Segment Sync Recovery block diagram. At
first input signal is integrated by the segment
passing through Segment Correlator. Slicer extracts
the information of Data Segment Sync interval
from output of integration period. This information
undergoes its reliability check in Confidence
Counter and then creates Data Segment Sync.
When reliability builds up to some level, nSegLock
signal is generated to inform the completion of
Data Segment Sync Recovery. This signal can read
through I²C bus(nSegLock in I²C bus register8).
output of Polarity correct
Segment
Correlator
Segment
Integrator
Segment
Slicer
Confidence
Counter
nSegLock
nSegSync
control signal
Figure 6.3.8 The Block Diagram of Data Segment Sync Recovery
If Data Segment Sync is found in this block, input
polarity is detected in the Polarity Decision block
and Timing Recovery block sets SEGSYNCLOCK
signal to ‘1’ which informs the start of activation
(Timing recovery start status). This signal is ‘0’
until it finds Data Segment Sync.
41