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| GDC21D003 Datasheet, PDF (69/77 Pages) Hynix Semiconductor – VSB Receiver | |||
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GDC21D003
VSBCLK
VSBSOP
VSBDVALID
NVSBERRFLG
VSBDATA[7:0]
polarity is inverted
with error
47H byte0 byte1
188
without error
byte186 0
0
20
47H byte0
Figure 6.6.11 I/F to Transport Demultiplexer when Register64[1] is set to â 0â
If only I2C register64[0](Vsbclk_sup) is set to â0â and other values are reserved as the default,
1) the VSBCLK signal is suppressed to â0â during VSBDVALID=â0â interval. See Fig. 6.6.12.
VSBCLK
VSBSOP
suppressed to â0â
VSBDVALID
NVSBERRFLG
VSBDATA[7:0]
with error
47H byte0 byte1
188
without error
byte186 0
0
20
47H byte0
Figure 6.6.12 I/F to Transport Demultiplexer when Register64[0](Vsbclk_sup) is set to â 0â
At MMDS 8VSB mode, the duty cycle of VSBCLK is not 50% of VSBCLK period. Since 8 symbols compose 3
bytes, the duration of first byte equals to those of two symbols, and the duration of second and third byte is 3
symbols each. See Fig. 6.6.13.
70
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