GDC21D003 Datasheet, PDF (39/77 Pages) Hynix Semiconductor – VSB Receiver

GDC21D003
Input Selection
DC Reduction
+
-
Accumulator
AGC offset
Coherent AGC
PWM
Non-Choerent
AGC
RESET
GUP
GDN
Figure 6.3.5 The Block Diagram of AGC
GUP/GDN signal is transmitted to off-chip
demodulator and controls the gain of Tuner and
demodulator.
Through I²C bus, AGC block can be held(When
AGChold signal in register0 is ‘1’). And for input
data to have desired optimum value, Coherent
AGC uses reference value which can be input
through I²C bus (AGCoffset[7:0] in I²C bus
register1) or can use already defined value. If you
want to change Coherent AGC reference value
through I²C bus, AGCoffset[7:0](in I²C bus
register1) value should be set and AGCoffsetW(in
register0) signal should be set to ‘1’. If
AGCoffsetW signal is ‘0’, already defined value is
used as a reference value. Figure 6.6 shows the
connection of chip output, GUP/GDN signal.
TUNER
LA7785M
(SANYO)
GDC21D003
(LG)
(NOTE) RFAGC signal, an input signal to Tuner should be connected referring to LA7785M.
Figure 6.3.6 AGC Signal I/F for DTV System
6.3.4 Polarity Correction
For currently used demodulator algorithm,
FPLL(Frequency & Phase Locked Loop) is used.
Due to FPLL algorithm’s property, demodulator
(carrier recovery) lock can occur in 0^o phase(in
phase) or 180^ophase(out of phase). When carrier is
locked in 0^o phase, there is no problem, but when
carrier is locked in 180^o phase, polarity of baseband
data are all inverted. In this case, input data
polarity should be reverted.
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