GDC21D003 Datasheet, PDF (19/77 Pages) Hynix Semiconductor – VSB Receiver

GDC21D003
5.3 I²C Bus Register Description
Address 0:
Most significant bit (MSB) inversion control signal of data input (DIN[9:0]).
7
Dinmode
W
If data input form is unsigned, the MSB of digital data input should be inverted
because all of functions in this chip use their complement data. If this bit is set
to ‘1’, it indicates the inversion of MSB. Initial value is ‘1’. (refer to table 6.3.1)
6
Dinsel
W
Digital data input path selection signal. If this bit is set to ‘1’, it indicates output
of the internal ADC. Initial value is ‘1’. (refer to table 6.3.1)
ADC Clock Select. When the frequency of VCXO is 2fs(21.52MHz), the output
5
ADCCLKSEL
W
frequency of ADCCLK can be one of the two following frequencies,
fs(10.76MHz) and 2fs. If this bit is set to ‘1’, the frequency of ADCCLK is
always fs. Initial value is ‘1’. (refer to table 6.2.1)
ADC Clock Phase Select. This signal can choose one of the ADCCLK output
4
ADCCLKPH
W
phases. If this bit is set to ‘0’, the ADCCLK output phase is rotated 180^° off with
respect to CLKFS phase, and otherwise 0°. Default value is ‘1’. (refer to table
6.2.1)
3
DCbypass
W DC remove block bypass (active high). Initial value is ‘0’.
2
DChold
W DC remove block hold (active high). Initial value is ‘0’.
1
AGChold
W AGC block hold (active high). Initial value is ‘0’.
0
AGCoffsetW W AGC offset write enable (active high). Initial value is ‘0’.
Address 1:
[7:0]
AGCoffset
[7:0]
W
AGC offset value. If AGCoffsetW is set to ‘1’, this signal is used for the
reference of AGC block. Default value is “01100000”.
Address 2:
[7:5]
VSB mode signal. If VSBmodW is set to ‘1’, this signal is used for VSB mode
VSBmod[2:0] W signal. Otherwise the VSBmod[2:0] signal is generated internally. Initial value
is “101”.
[4:0]
W Initial value is “10010”. It would be better set to “10110”.
Address 3:
[7:0]
W Always set to “11001000”.
20