GDC21D003 Datasheet, PDF (5/77 Pages) Hynix Semiconductor – VSB Receiver

GDC21D003
Figure 6.3.16 The Block Diagram of NTSC Rejection ............................................................ 49
Figure 6.4.1 Channel Equalizer ........................................................................................... 50
Figure 6.4.2 VSB Slicer ....................................................................................................... 51
Figure 6.4.3 Training/Data Equalization .............................................................................. 51
Figure 6.4.4 VSB Slice Level .............................................................................................. 52
Figure 6.4.5 Coefficient Update Filter ................................................................................. 53
Figure 6.4.6 I²C Bus I/F ....................................................................................................... 54
Figure 6.5.1 Phase Tracker ................................................................................................. 57
Figure 6.5.2 Error Detection ................................................................................................ 57
Figure 6.5.3 Coefficients of Hilbert Transform Filter ........................................................... 58
Figure 6.5.4 Complex Multiplier .......................................................................................... 58
Figure 6.6.1 Block Diagram of Channel Decoder ............................................................... 60
Figure 6.6.2 12-Symbol Intrasegment Deinterleaver .......................................................... 61
Figure 6.6.3 Segment Sync Suspension ............................................................................. 62
Figure 6.6.4 Viterbi Decoding with and without NTSC Rejection Filter ............................... 63
Figure 6.6.5 Internal Block Diagram of Viterbi Decoder ...................................................... 63
Figure 6.6.6 Convolutional Deinterleaver ............................................................................ 65
Figure 6.6.7 Derandomizer Polynomial ............................................................................... 66
Figure 6.6.8 I/F to Transport Demultiplexer when Register64[7:0] is set to
Default Value .................................................................................................... 68
Figure 6.6.9 I/F to Transport Demultiplexer when Register64[3] (Derand_on)
is set to ‘ 0’ ........................................................................................................ 69
Figure 6.6.10 I/F to Transport Demultiplexer when Register64[2](Errorflg_ins)
is set to ‘ 0’ ........................................................................................................ 69
Figure 6.6.11 I/F to Transport Demultiplexer when Register64[1](Vsbdvalid_pol)
is set to ‘ 0’ ........................................................................................................ 70
Figure 6.6.12 I/F to Transport Demultiplexer when Register64[0](Vsbclk_sup)
is set to ‘ 0’ ........................................................................................................ 70
Figure 6.6.13 I/F to Transport Demultiplexer(MMDS 8VSB Mode) ....................................... 71
Figure 6.6.14 I/F to Transport Demultiplexer at Serial Output Mode ..................................... 71
Figure 6.6.15 Connection with VSB Receiver and Transport Demultiplexer
Chip(GDC21D301A) ........................................................................................ 72
Figure 6.6.16 Connection with VSB Receiver and Transport Demultiplexer
Chip(L64007) ................................................................................................... 72
Figure 6.6.17 Connection with VSB Receiver and Transport Demultiplexer
Chip(AVIA-MAX) .............................................................................................. 73
Figure 6.7.1 Clock Scheme ................................................................................................. 74
Figure 7.1 Clock Reset Stabilization Timing ..................................................................... 76
Figure 7.2 Input and Output Timing .................................................................................. 76
Figure 8.1 Physical Dimensions ........................................................................................ 77
Figure 9.1 VSB Receiver Application Circuit ..................................................................... 78
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