GDC21D003 Datasheet, PDF (31/77 Pages) Hynix Semiconductor – VSB Receiver

6.1.2 Timing Diagram
SYMCLK
GDC21D003
Analog
Input
N
N+1
N+2
N+3
N+4
Data
Output
32
N-3
N-2
N-1
N
N+1
: TDL Output Delay
¡ Ü : Analog Input Sampling Point
TDL =3ns
Figure 6.1.2 Timing Diagram of ADC