GDC21D003 Datasheet, PDF (44/77 Pages) Hynix Semiconductor – VSB Receiver

Phase information from chip passes through
Charge Pump and is input to Loop Filter. Loop
Filter output is connected to VCXO to control
clock phase. Figure 6.3.11 shows the connection
diagram when external VCXO output frequency is
GDC21D003
equal to 1 and 2 times output frequency of symbol
frequency. And Figure 6.3.12 shows the connection
diagram when external VCXO output frequency is
equal to that of symbol frequency.
56
NCHGUP
GDC21D003
(LG)
57
NCHGDN
+3.3V
Analog
S/W
Analog
S/W
10K
VCXO
Charge Pump
Loop Filter
10.76MHz
OPEN
Or
To ADC
OPEN
(NOTE) - ADCCLK frequency and CLKFS phase should be set as Table 6.2.1 when digital input using external ADC
is used.
- Each discrete device value in this figure is just recommended value.
- Analog S/W should be ON when input signal (NCHGUP/NCHGDN) is ‘0’.
- PNP type transistor can be used instead of Analog S/W.
Figure 6.3.12 Timing Recovery I/F Circuit(2)
45