GDC21D003 Datasheet, PDF (7/77 Pages) Hynix Semiconductor – VSB Receiver

G^GD^DC^C2²1¹D^D0⁰0⁰3³
VSB Receiver
1. General Description
The VSB Receiver(GDC21D003) is an ATSC
compliant single chip communications device that
synchronizes, equalizes, and corrects errors of
ATSC 8/16 VSB and MMDS (Multichannel
Multipoint Distribution System) 2/4/8/16 VSB
modulated signal.
The on-chip 10-bit 10.76Msps Analog-to-Digital
Converter has an input sample-and-hold amplifier.
By implementing a multistage pipelined
architecture with output correction logic, the ADC
offers accurate performance and guarantees no
missing codes over the full operating temperature.
Clock divider divides output clock of external
VCXO and generates symbol clock (CLKFS) and
ADCCLK. The CLKFS has 10.76MHz frequency
as symbol frequency used in DTV transmitter,
ADCCLK is used for external A/D converter. At
this time, if you use digital signal as input of chip,
CLKFS or ADCCLK are used for external A/D
converter clock.
Synchronizer removes DC entered from transmitter
and DC generated by analog circuit used in
receiver. Also it checks gain of input signal and
sends it to demodulator, detects polarity, and
corrects it. It recovers Data Segment Sync period
and Field Sync period entered from transmitter. It
detects VSB mode of current input signal and
removes NTSC co-channel interference in channel.
Equalizer corrects linear distortion created during
transmission. It uses Least-Mean-Square algorithm
and has decision feedback equalizer structure. It
uses adaptive filter having coefficient update
structure consisted of multiplier, adder, and
memory structure in every tap.
Phase Tracker compensates phase distortion due to
phase noise and it consists of gain correction loop
for gain error, offset correction loop for offset error,
and phase correction loop for phase error.
Channel Decoder consists of Viterbi Decoder,
Convolutional Deinterleaver, Reed-Solomon
Decoder, Data Derandomizer, and etc. It decodes
ATSC 8/16 VSB signal and MMDS 2/4/8/16 VSB
signal. Also it has internal segment error counter
that send out the number of segment errors per
second and offers tri-state parallel/serial Transport
Demultiplexer interface.
2. Features
General features
• ATSC compliant 8/16 VSB receiver
• MMDS 2/4/8/16 VSB receiver
• SNR threshold 14.9 dB on AWGN channel
• Tri-state parallel/serial MPEG-2 transport
interface
• Supports I²C bus interface
• Boundary Scan Test circuit complies with
IEEE Std. 1149.1
ID-Code = 0D0031C1
• Operating voltage : 3.3V
• 0.35µm CMOS technology
• 128 pin HQFP package
ADC
• Resolution : 10bits (≤ ±¹â„₂ LSB DNL error)
• Sampling rate : 10.76 Msps
• Differential input range : 2Vpp(1.7 ± 0.5V
differential)
Clock Divider
• Generates symbol clock(10.76MHz)
• Uses one of two VCXOs, fs(10.76MHz) and
2fs(21.52MHz) as input
Synchronizer
• Input control
• DC reduction and polarity correction
- Correction of polarity ambiguity caused
by FPLL
• Non-coherent and coherent automatic gain
control (AGC)
• Data Segment Sync and Field Sync recovery
• Timing recovery
• Polarity decision
- Polarity decision after Data Segment
Sync is locked
• VSB mode detection
• Comb control
- Comb filter for the rejection of NTSC
co-channel interface
8