MC68HC05B6_13 Datasheet, PDF (98/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
Note:
The bits that are shown shaded in the above representation are explained individually
in the relevant sections of this manual. The complete register plus an explanation of
each bit can be found in Section 3.8
7.2
PLM clock selection
The slow/fast mode of the PLM D/A converters is selected by bits 1, 2, and 3 of the miscellaneous
register at address $000C (SFA bit for PLMA and SFB bit for PLMB). The slow/fast mode has no
effect on the D/A converters’ 8-bit resolution (see Figure 7-3).
f_OSC
7
Bus
Timer
÷2
SM bit = 0
frequency (f_OP) _÷4 clock _x4096 ^{SF bit = 1}
PLM
clock
÷32 ^{SM bit = 1}
x256 ^{SF bit = 0}
Figure 7-3 PLM clock selection
7.3
PLM during STOP mode
On entering STOP mode, the PLM outputs remain at their particular level. When STOP mode is
exited by an interrupt, the PLM systems resume regular operation. If STOP mode is exited by
power-on or external reset the registers values are forced to $00.
7.4
PLM during WAIT mode
The PLM system is not affected by WAIT mode and continues normal operation.
Freescale
7-4
PULSE LENGTH D/A CONVERTERS
MC68HC05B6
Rev. 4.1