MC68HC05B6_13 Datasheet, PDF(52/302 Page) Freescale Semiconductor, Inc – Microcontrollers

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MC68HC05B6_13 Datasheet, PDF (52/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

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SFA â Slow or fast mode selection for PLMA (see Section 7.1)

This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation

output.

1 (set) â Slow mode PLMA (4096 x timer clock period).

3

0 (clear) â Fast mode PLMA (256 x timer clock period).

SFB â Slow or fast mode selection for PLMB (see Section 7.1)

This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation

output.

1 (set) â Slow mode PLMB (4096 x timer clock period).

0 (clear) â Fast mode PLMB (256 x timer clock period).

Note:

The highest speed of the PLM system corresponds to the frequency of the TOF bit

being set, multiplied by 256. The lowest speed of the PLM system corresponds to the

frequency of the TOF bit being set, multiplied by 16.

Warning: Because the SFA bit and SFB bit are not double buffered, it is mandatory to set the SFA

bit and SFB bit to the desired values before writing to the PLM registers; not doing so

could temporarily give incorrect values at the PLM outputs.

SM â Slow mode (see Section 2.4.3)

1 (set)

â The system runs at a bus speed 16 times lower than normal

(fOSC/32). SLOW mode affects all sections of the device, including

SCI, A/D and timer.

0 (clear) â The system runs at normal bus speed (fOSC/2).

The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when

entering STOP mode.

WDOG â Watchdog enable/disable (see Section 9.1.4)

The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.

Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.

Once the watchdog is enabled, the WDOG bit acts as a reset mechanism for the watchdog

counter. Writing aâ1â to this bit clears the counter to its initial value and prevents a watchdog

timeout.

1 (set) â Watchdog counter cleared and enabled.

0 (clear) â The watchdog cannot be disabled by software; writing a zero to this

bit has no effect.

Freescale

3-10

MEMORY AND REGISTERS

MC68HC05B6

Rev. 4.1

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