MC68HC05B6_13 Datasheet, PDF (86/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

6.11.3 Serial communications control register 2 (SCCR2)
The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI
functions.
SCI control (SCCR2)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000
TIE — Transmit interrupt enable
1 (set) – TDRE interrupts enabled.
0 (clear) – TDRE interrupts disabled.
TCIE — Transmit complete interrupt enable
6
1 (set) – TC interrupts enabled.
0 (clear) – TC interrupts disabled.
RIE — Receiver interrupt enable
1 (set) – RDRF and OR interrupts enabled.
0 (clear) – RDRF and OR interrupts disabled.
ILIE — Idle line interrupt enable
1 (set) – IDLE interrupts enabled.
0 (clear) – IDLE interrupts disabled.
TE — Transmitter enable
When the transmit enable bit is set, the transmit shift register output is applied to the TDO line and
the corresponding clocks are applied to the SCLK pin. Depending on the state of control bit M
(SCCR1), a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones is transmitted when software
sets the TE bit from a cleared state.
If a transmission is in progress and a zero is written to TE, the transmitter will wait until after the
present byte has been transmitted before placing the TDO and the SCLK pin in the idle, high
impedance state.
If the TE bit has been written to a zero and then set to a one before the current byte is transmitted,
the transmitter will wait for that byte to be transmitted and will then initiate transmission of a new
preamble. After this latest transmission, and provided the TDRE bit is set (no new data to
transmit), the line remains idle (driven high while TE = 1); otherwise, normal transmission occurs.
This function allows the user to neatly terminate a transmission sequence.
Freescale
6-14
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4.1