MC68HC05B6_13 Datasheet, PDF (84/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

CPOL – Clock polarity
This bit allows the user to select the polarity of the clocks to be sent to the SCLK pin. It works in
conjunction with the CPHA bit to produce the desired clock-data relation (see Figure 6-9 and
Figure 6-10).
1 (set) – Steady high value at SCLK pin outside transmission window.
0 (clear) – Steady low value at SCLK pin outside transmission window.
This bit should not be manipulated while the transmitter is enabled.
CPHA – Clock phase
This bit allows the user to select the phase of the clocks to be sent to the SCLK pin. This bit works
in conjunction with the CPOL bit to produce the desired clock-data relation (see Figure 6-9 and
Figure 6-10).
6
1 (set) – SCLK clock line activated at beginning of data bit.
0 (clear) – SCLK clock line activated in middle of data bit.
This bit should not be manipulated while the transmitter is enabled.
Idle or preceding
transmission _Start
clock
(CPOL = 0, CPHA = 0)
clock
(CPOL = 0, CPHA = 1)
clock
(CPOL = 1, CPHA = 0)
clock
(CPOL = 1, CPHA = 1)
data
01
Start LSB
M = 0 (8 data bits)
Idle or next
Stop transmission
*
*
*
*
234567
MSB Stop
* LBCL bit controls last data clock
Figure 6-9 SCI data clock timing diagram (M=0)
Freescale
6-12
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4.1