MC68HC05B6_13 Datasheet, PDF (125/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

Table 10-8 Instruction set (2 of 2)
Mnemonic
COM
CPX
DEC
EOR
INC
JMP
JSR
LDA
LDX
LSL
LSR
MUL
NEG
NOP
ORA
ROL
ROR
RSP
RTI
RTS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT
Addressing modes
INH IMM DIR EXT REL IX IX1
Condition codes
IX2 BSC BTB H I N Z C
• • ÞÞ1
• • ÞÞÞ
• • ÞÞ •
• • ÞÞ •
• • ÞÞ •
•••••
•••••
• • ÞÞ •
• • ÞÞ •
• • ÞÞÞ
• • 0ÞÞ
0• • •0
• • ÞÞÞ
•••••
• • ÞÞ •
• • ÞÞÞ
• • ÞÞÞ
•••••
?????
•••••
• • ÞÞÞ
• • • •1
•1• • •
• • ÞÞ •
•0• • •
• • ÞÞ •
• • ÞÞÞ
•1• • •
•••••
• • ÞÞ •
•••••
•0• • •
Address mode abbreviations
BSC Bit set/clear
IMM Immediate
BTB Bit test & branch
IX Indexed (no offset)
DIR Direct
IX1 Indexed, 1 byte offset
EXT Extended
IX2 Indexed, 2 byte offset
INH Inherent
REL Relative
Not implemented
Condition code symbols
H Half carry (from bit 3)
Þ
Tested and set if true,
cleared otherwise
I Interrupt mask
• Not affected
N Negate (sign bit)
? Load CCR from stack
Z Zero
0 Cleared
C Carry/borrow
1 Set
10
MC68HC05B6
Rev. 4.1
CPU CORE AND INSTRUCTION SET
Freescale
10-9