MC68HC05B6_13 Datasheet, PDF (250/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

14
Table G-1 Register outline
Register name
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
Port D data (PORTD)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
EEPROM/ECLK control
A/D data (ADDATA)
A/D status/control (ADSTAT)
Pulse length modulation A (PLMA)
Pulse length modulation B (PLMB)
Miscellaneous
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
Options (OPTR)⁽³⁾
Mask option register (MOR)⁽⁴⁾
Address bit 7 bit 6
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0100
$7FDE
PD7
0
COCO
POR⁽¹⁾
SPC1
R8
TIE
TDRE
ICIE
ICF1
PD6
0
ADRC
INTP
SPC0
T8
TCIE
TC
OCIE
OCF1
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State on
reset
Undefined
Undefined
PC2/
ECLK
Undefined
PD5 PD4 PD3 PD2 PD1 PD0 Undefined
0000 0000
0000 0000
0000 0000
0
0 ECLK E1ERA E1LAT E1PGM 0000 0000
0000 0000
ADON 0 CH3 CH2 CH1 CH0 0000 0000
0000 0000
0000 0000
INTN INTE SFA SFB SM WDOG⁽²⁾ ?001 000?
SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
M WAKE CPOL CPHA LBCL Undefined
RIE ILIE TE RE RWU SBK 0000 0000
RDRF IDLE OR NF FE
1100 000u
0000 0000
TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
TOF ICF2 OCF2
Undefined
Undefined
Undefined
Undefined
Undefined
1111 1111
1111 1100
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
EE1P SEC Not affected
RTIM RWAT WWAT PBPD PCPD Not affected
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1 = watchdog enabled, 0 = watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
(4) This register is implemented in ROM; therefore reset has no effect on the individual bits.
Freescale
G-4
MC68HC05B32
MC68HC05B6
Rev. 4.1