MC68HC05B6_13 Datasheet, PDF (154/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

Table A-2 Register outline
Register name
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State on
reset
Port A data (PORTA)
$0000
Undefined
Port B data (PORTB)
$0001
Undefined
Port C data (PORTC)
$0002
PC2/
ECLK
Undefined
Port D data (PORTD)
$0003 PD7/ PD6/ PD5/ PD4/ PD3/ PD2/ PD1/ PD0/ Undefined
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
Port A data direction (DDRA)
$0004
0000 0000
Port B data direction (DDRB)
$0005
0000 0000
Port C data direction (DDRC)
$0006
0000 0000
ECLK control
$0007 0
0
0
0 ECLK 0
0
0 0000 0000
A/D data (ADDATA)
$0008
0000 0000
A/D status/control (ADSTAT)
$0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000
Pulse length modulation A (PLMA) $000A
0000 0000
Pulse length modulation B (PLMB) $000B
0000 0000
Miscellaneous
$000C POR⁽¹⁾ INTP INTN INTE SFA SFB SM WDOG ?001 000?
(2)
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
SPC1
R8
TIE
TDRE
ICIE
ICF1
SPC0
T8
TCIE
TC
OCIE
OCF1
SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
M WAKE CPOL CPHA LBCL uuuu uuuu
RIE ILIE TE RE RWU SBK 0000 0000
RDRF IDLE OR NF FE
1100 000u
0000 0000
TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
TOF ICF2 OCF2
uuuu uuuu
Undefined
Undefined
Undefined
Undefined
1111 1111
1111 1100
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
14
Freescale
A-4
MC68HC05B4
MC68HC05B6
Rev. 4.1