MC68HC05B6_13 Datasheet, PDF (121/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

Table 10-1 MUL instruction
Operation
Description
Condition
codes
Source
Form
X:A ← X*A
Multiplies the eight bits in the index register by the eight
bits in the accumulator and places the 16-bit result in the
concatenated accumulator and index register.
H : Cleared
I : Not affected
N : Not affected
Z : Not affected
C : Cleared
MUL
Addressing mode Cycles Bytes Opcode
Inherent
11
1
$42
Function
Load A from memory
Load X from memory
Store A in memory
Store X in memory
Add memory to A
Add memory and carry to A
Subtract memory
Subtract memory from A
with borrow
AND memory with A
OR memory with A
Exclusive OR memory with A
Arithmetic compare A
with memory
Arithmetic compare X
with memory
Bit test memory with A
(logical compare)
Jump unconditional
Jump to subroutine
Table 10-2 Register/memory instructions
Immediate
Direct
Addressing modes
Extended
Indexed
(no
offset)
Indexed
(8-bit
offset)
Indexed
(16-bit
offset)
LDA A6 2 2 B6 2 3 C6 3 4 F6 1 3 E6 2 4 D6 3 5
LDX AE 2 2 BE 2 3 CE 3 4 FE 1 3 EE 2 4 DE 3 5
STA
B7 2 4 C7 3 5 F7 1 4 E7 2 5 D7 3 6
STX
BF 2 4 CF 3 5 FF 1 4 EF 2 5 DF 3 6
ADD AB 2 2 BB 2 3 CB 3 4 FB 1 3 EB 2 4 DB 3 5
ADC A9 2 2 B9 2 3 C9 3 4 F9 1 3 E9 2 4 D9 3 5
SUB A0 2 2 B0 2 3 C0 3 4 F0 1 3 E0 2 4 D0 3 5
SBC A2 2 2 B2 2 3 C2 3 4 F2 1 3 E2 2 4 D2 3 5
AND A4 2 2 B4 2 3 C4 3 4 F4 1 3 E4 2 4 D4 3 5
ORA AA 2 2 BA 2 3 CA 3 4 FA 1 3 EA 2 4 DA 3 5
EOR A8 2 2 B8 2 3 C8 3 4 F8 1 3 E8 2 4 D8 3 5
CMP A1 2 2 B1 2 3 C1 3 4 F1 1 3 E1 2 4 D1 3 5
CPX A3 2 2 B3 2 3 C3 3 4 F3 1 3 E3 2 4 D3 3 5
BIT A5 2 2 B5 2 3 C5 3 4 F5 1 3 E5 2 4 D5 3 5
JMP
BC 2 2 CC 3 3 FC 1 2 EC 2 3 DC 3 4
JSR
BD 2 5 CD 3 6 FD 1 5 ED 2 6 DD 3 7
10
MC68HC05B6
Rev. 4.1
CPU CORE AND INSTRUCTION SET
Freescale
10-5