MC68HC05B6_13 Datasheet, PDF (74/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

6
Internal bus
$0011 Transmit
(See note) data register
SCI interrupt
+
$0011 Receive
(See note) data register
&
&
&
&
$000F
SCCR2
TDO
pin
Transmit
data shift
register
+
SCSR
TIE
TCIE
RIE
ILIE
7
6
5
4
Receive
data shift
register
RDI
pin
TE
3
RE
2
SBK 1
RWU 0
$0010
7
6
5
4
32
1
TRDE TC RDRF IDLE OR NF FE
Wake up
unit
TE
SBK
7
Transmitter
control
Transmitter
clock
Flag
control
Receiver
control
Receiver
clock
SCLK
pin
Clock extraction
phase and
polarity control
7
65
R8
T8
4
32
1
0 SCCR1
M WAKE CPOL CPHA LBCL $000E
Note:
The serial communications data register (SCI SCDR) is controlled by the internal
R/W signal. It is the transmit data register when written to and the receive data
register when read.
Figure 6-1 Serial communications interface block diagram
Freescale
6-2
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4.1