MC68HC05B6_13 Datasheet, PDF (37/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

2.4.3 SLOW mode
The SLOW mode function is controlled by the SM bit in the miscellaneous register at location
2
$000C. It allows the user to insert, under software control, an extra divide-by-16 between the
oscillator and the internal clock driver (see Figure 2-4). This feature permits a slow down of all the
internal operations and thus reduces power consumption. The SLOW mode function should not
be enabled while using the A/D converter or while erasing/programming the EEPROM unless the
internal A/D RC oscillator is turned on.
OSC1
pin
OSC2
pin
Oscillator
f_OSC
f_OSC/2
÷2
÷ 16
f_OSC/32
SM–bit
(bit 1, $000C)
Control logic
Figure 2-4 Slow mode divider block diagram
Main internal clock
2.4.3.1 Miscellaneous register
Miscellaneous
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000C POR INTP INTN INTE SFA SFB SM WDOG ?001 000?
SM — Slow mode
1 (set)
– The system runs at a bus speed 16 times lower than normal
(f_OSC/32). SLOW mode affects all sections of the device, including
SCI, A/D and timer.
0 (clear) – The system runs at normal bus speed (f_OSC/2).
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
Note:
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
MC68HC05B6
Rev. 4.1
MODES OF OPERATION AND PIN DESCRIPTIONS
Freescale
2-9