MC68HC05B6_13 Datasheet, PDF (81/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

6.10
SCI synchronous transmission
The SCI transmitter allows the user to control a one way synchronous serial transmission. The
SCLK pin is the clock output of the SCI transmitter. No clocks are sent to that pin during start bit
and stop bit. Depending on the state of the LBCL bit (bit 0 of SCCR1), clocks will or will not be
activated during the last valid data bit (address mark). The CPOL bit (bit 2 of SCCR1) allows the
user to select the clock polarity, and the CPHA bit (bit 1 of SCCR1) allows the user to select the
phase of the external clock (see Figure 6-8, Figure 6-9 and Figure 6-10).
During idle, preamble and send break, the external SCLK clock is not activated.
These options allow the user to serially control peripherals which consist of shift registers, without
losing any functions of the SCI transmitter which can still talk to other SCI receivers. These options
do not affect the SCI receiver which is independent of the transmitter.
The SCLK pin works in conjunction with the TDO pin. When the SCI transmitter is disabled
(TE = 0), the SCLK and TDO pins go to the high impedance state.
6
Note:
The LBCL, CPOL and CPHA bits have to be selected before enabling the transmitter
to ensure that the clocks function correctly. These bits should not be changed while the
transmitter is enabled.
RDI
TDO
SCLK
MC68HC05B6
Output port
Data out
Data in
Data in
Clock
Enable
Asynchronous
(e.g. Modem)
Synchronous
(e.g. shift register,
display driver, etc.)
Figure 6-8 SCI example of synchronous and asynchronous transmission
MC68HC05B6
Rev. 4.1
SERIAL COMMUNICATIONS INTERFACE
Freescale
6-9