MC68HC05B6_13 Datasheet, PDF (76/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

When SCDR is read, it contains the last data byte received, provided that the receiver is enabled.
The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has
been transferred from the input serial shift register to the SCDR; this will cause an interrupt if the
receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is
synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error
flags in the SCSR may be set if data reception errors occurred.
An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects
idle line transmission) in SCSR is set. This allows a receiver that is not in the wake-up mode to
detect the end of a message or the preamble of a new message, or to resynchronize with the
transmitter. A valid character must be received before the idle line condition or the IDLE bit will not
be set and idle line interrupt will not be generated.
The SCP0 and SCP1 bits function as a prescaler for SCR0–SCR2 to generate the receiver baud rate
and for SCT0–SCT2 to generate the transmitter baud rate. Together, these eight bits provide multiple
transmitter/receiver rate combinations for a given crystal frequency (see Figure 6-2). This register
6
should only be written to while both the transmitter and receiver are disabled (TE=0, RE=0).
Internal processor clock
SCP0 – SCP1
prescaler
rate control
(÷ NP)
SCT0 – SCT2
transmitter
rate control
(÷ NT)
SCR0 – SCR2
receiver
rate control
(÷ NR)
÷16
Transmitter clock
SCP1 SPC0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 _$000D
7
6
5
4
3
2
1
0
Baud rate register
Receiver clock
Note:
There is a fixed rate divide-by-16 before the transmitter to compensate for the inherent divide-by-16 of the receiver (sampling).
This means that by loading the same value for both the transmitter and receiver baud rate selector, the same baud rates can
be obtained.
Figure 6-2 SCI rate generator division
Freescale
6-4
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4.1