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MC68HC05B6_13 Datasheet, PDF (282/302 Pages) Freescale Semiconductor, Inc – Microcontrollers
I.1
DC electrical characteristics
Table I-2 DC electrical characteristics for 5V operation
(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output voltage
ILOAD = – 10 µA
ILOAD = +10 µA
Output high voltage (ILOAD = 0.8mA)
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2
Output high voltage (ILOAD = 1.6mA)
TDO, SCLK, PLMA, PLMB
Output low voltage (ILOAD = 1.6mA)
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
TDO, SCLK, PLMA, PLMB
Output low voltage (ILOAD = 1.6mA)
RESET
VOH
VDD – 0.1
—
—
V
VOL
—
—
0.1
VOH
VDD – 0.8
—
—
—
V
VOH
VDD – 0.8
—
—
VOL
—
—
VOL
—
—
—
0.4
V
—
1
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
VIH
0.7VDD
—
VDD
V
Input low voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,
RESET, TCAP1, TCAP2, RDI
Supply current(3)
RUN (SM = 0) (See Figure 11-1)
RUN (SM = 1) (See Figure 11-2)
WAIT (SM = 0) (See Figure 11-3)
WAIT (SM = 1) (See Figure 11-4)
STOP
0 to 70 (standard)
– 40 to 85 (extended)
VIL
VSS
—
0.2VDD
V
—
—
12
mA
—
—
3
mA
IDD
—
—
—
—
4
mA
2
mA
—
—
10
µA
—
—
20
µA
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK
Input current (0 to 70)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
IIL
—
—
±1
µA
IIN
—
—
±5
µA
—
±1
Capacitance
Ports (as input or output), RESET, TDO, SCLK
COUT
—
IRQ, TCAP1, TCAP2, OSC1, RDI
CIN
—
PD0/AN0–PD7/AN7 (A/D off)
CIN
—
PD0/AN0–PD7/AN7 (A/D on)
CIN
—
—
12
pF
—
8
pF
12
—
pF
22
—
pF
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient
switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 8.0MHz); all inputs 0.2 V from
rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with
OSC1 = VDD.
WAIT IDD is affected linearly by the OSC2 capacitance.
15
Freescale
I-2
HIGH SPEED OPERATION
MC68HC05B6
Rev. 4.1