MC68HC05B6_13 Datasheet, PDF (97/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

Note:
Since the PLM system uses the timer counter, PLM results will be affected while resetting
the timer counter. Both D/A registers are reset to $00 during power-on or external reset.
WAIT mode does not affect the output waveform of the D/A converters.
7.1
Miscellaneous register
Miscellaneous
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000C POR INTP INTN INTE SFA SFB SM WDOG ?001 000?
SFA — Slow or fast mode selection for PLMA
This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation
output.
1 (set) – Slow mode PLMA (4096 x timer clock period).
0 (clear) – Fast mode PLMA (256 x timer clock period).
7
SFB — Slow or fast mode selection for PLMB
This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation
output.
1 (set) – Slow mode PLMB (4096 x timer clock period).
0 (clear) – Fast mode PLMB (256 x timer clock period).
The highest speed of the PLM system corresponds to the frequency of the TOF bit being set,
multiplied by 256. The lowest speed of the PLM system corresponds to the frequency of the TOF
bit being set, multiplied by 16. Because the SFA bit and SFB bit are not double buffered, it is
mandatory to set them to the desired values before writing to the PLM registers; not doing so could
temporarily give incorrect values at the PLM outputs.
SM — Slow mode
1 (set)
– The system runs at a bus speed 16 times lower than normal
(f_OSC/32). SLOW mode affects all sections of the device, including
SCI, A/D and timer.
0 (clear) – The system runs at normal bus speed (f_OSC/2).
MC68HC05B6
Rev. 4.1
PULSE LENGTH D/A CONVERTERS
Freescale
7-3