MC68HC05B6_13 Datasheet, PDF (271/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

t_CR
Preliminary ^Address
PC5 out
Data
PC6 in
t_HO
t_ADR
t_DHR
t_HI max
Preliminary ^PD4
t_EXR max
t_ADR max (address to data delay; PC6=PC5)
t_DHR min (data hold time)
t_CR (load cycle time; PC6=PC5)
t_HO (PC5 handshake out delay)
t_HI max (PC6 handshake in, data hold time)
t_EXR max (max delay for transition to be recognised during this cycle; PC6=PC5
1 machine cycle = 1/(2f₀(Xtal))
16 machine cycles
4 machine cycles
49 machine cycles
5 machine cycles
10 machine cycles
30 machine cycles
Figure H-9 Parallel RAM loader timing diagram
Preliminary
14
MC68HC05B6
Rev. 4.1
MC68HC705B32
Freescale
H-21