MC68HC05B6_13 Datasheet, PDF (100/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

The A/D reference input (AN0–AN7) is applied to a precision internal D/A converter. Control logic
drives this D/A converter and the analog output is successively compared with the analog input
sampled at the beginning of the conversion. The conversion is monotonic with no missing codes.
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
VRH
(VRH+VRL)/2
VRL
8
8-bit capacitive DAC
with sample and hold
VRH
VRL
Successive approximation
register (SAR) and control
Result
A/D status/control register (ADSTAT)$09
CH0 CH1 CH2 CH3 0 ADON ADRC COCO
A/D result register (ADDATA) $08
Figure 8-1 A/D converter block diagram
The result of each successive comparison is stored in the SAR and, when the conversion is
complete, the contents of the SAR are transferred to the read-only result data register ($08), and
the conversion complete flag, COCO, is set in the A/D status/control register ($09).
Warning: Any write to the A/D status/control register will abort the current conversion, reset the
conversion complete flag and start a new conversion on the selected channel.
At power-on or external reset, both the ADRC and ADON bits are cleared; thus the A/D is disabled.
Freescale
8-2
ANALOG TO DIGITAL CONVERTER
MC68HC05B6
Rev. 4.1