MC68HC05B6_13 Datasheet, PDF (117/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

10
CPU CORE AND INSTRUCTION SET
This section provides a description of the CPU core registers, the instruction set and the
addressing modes of the MC68HC05B6.
10.1
Registers
The MCU contains five registers, as shown in the programming model of Figure 10-1. The interrupt
stacking order is shown in Figure 10-2.
7
0
7
0
15
7
0
15
7
0
0000000011
7
0
111H I NZC
Accumulator
Index register
Program counter
Stack pointer
Condition code register
Carry / borrow
Zero
Negative
Interrupt mask
Half carry
10
Figure 10-1 Programming model
7
Increasing
memory
address
Unstack
Condition code register
Accumulator
Index register
Program counter high
Program counter low
0
Stack
Decreasing
memory
address
Figure 10-2 Stacking order
MC68HC05B6
Rev. 4.1
CPU CORE AND INSTRUCTION SET
Freescale
10-1