MC68HC05B6_13 Datasheet, PDF (54/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

Data direction
register bit
DDRn
Latched data
DATA
Output
I/O
register bit
buffer
Pin
4
dOa/tPa
DDRn DATA I/O Pin
buffer
1
0
0
Input
Output 

1
1
1
buffer
Input



0
0
0
tristate
1
tristate
Figure 4-1 Standard I/O port structure
Table 4-1 shows the effect of reading from or writing to an I/O pin in various circumstances. Note
that the read/write signal shown is internal and not available to the user.
Table 4-1 I/O pin states
R/W DDRn
Action of MCU write to/read of data bit
0
0 The I/O pin is in input mode. Data is written into the output data latch.
0
1 Data is written into the output data latch, and output to the I/O pin.
1
0 The state of the I/O pin is read.
1
1 The I/O pin is in output mode. The output data latch is read.
4.2
Ports A and B
These ports are standard M68HC05 bidirectional I/O ports, each comprising a data register and
a data direction register.
Reset does not affect the state of the data register, but clears the data direction register, thereby
returning all port pins to input mode. Writing a ‘1’ to any DDR bit sets the corresponding port pin
to output mode.
Freescale
4-2
INPUT/OUTPUT PORTS
MC68HC05B6
Rev. 4.1