MC68HC05B6_13 Datasheet, PDF (256/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

14
Table H-1 Register outline
Preliminary ^{Register name}
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
Port D data (PORTD)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
EPROM/EEPROM/ECLK control
A/D data (ADDATA)
A/D status/control (ADSTAT)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State on
reset
$0000
Undefined
$0001
Undefined
$0002
PC2/
ECLK
Undefined
$0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
$0004
0000 0000
$0005
0000 0000
$0006
0000 0000
$0007
0 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM u000 0000
$0008
0000 0000
$0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000
Pulse length modulation A (PLMA) $000A
0000 0000
Pulse length modulation B (PLMB) $000B
0000 0000
Miscellaneous
$000C POR⁽¹⁾ INTP INTN INTE SFA SFB SM WDOG⁽²⁾ ?001 000?
Preliminary ^{SCI baud rate (BAUD)}
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
SPC1
R8
TIE
TDRE
ICIE
ICF1
SPC0
T8
TCIE
TC
OCIE
OCF1
SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
M WAKE CPOL CPHA LBCL Undefined
RIE ILIE TE RE RWU SBK 0000 0000
RDRF IDLE OR NF FE
1100 000u
0000 0000
TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
TOF ICF2 OCF2
Undefined
Undefined
Undefined
Undefined
Undefined
1111 1111
Timer counter low
$0019
1111 1100
Alternate counter high
$001A
1111 1111
Alternate counter low
$001B
1111 1100
Preliminary ^{Input capture high 2}
Input capture low 2
Output compare high 2
Output compare low 2
Options (OPTR)⁽³⁾
Mask option register (MOR)⁽⁴⁾
$001C
$001D
$001E
$001F
$0100
$7FDE
RTIM
RWAT WWAT
EE1P
PBPD
Undefined
Undefined
Undefined
Undefined
SEC Not affected
PCPD Not affected
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
(4) This register is implemented in EPROM; therefore reset has no effect on the individual bits.
Freescale
H-6
MC68HC705B32
MC68HC05B6
Rev. 4.1