MC68HC05B6_13 Datasheet, PDF (263/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

H.5
Bootstrap mode
Preliminary ^{Oscillator divide-by-two is forced in bootstrap mode.}
The 432 bytes of self-check firmware on the MC68HC05B6 are replaced by 654 bytes of bootstrap
firmware. A detailed description of the modes of operation within bootstrap mode is given below.
The bootstrap program in mask ROM address locations $0200 to $024F, $03B0 to $3FFF, $7E00
to $7FDD and $7FE0 to $7FEF can be used to program the EPROM and the EEPROM, to check
if the EPROM is erased or to load and execute data in RAM.
After reset, while going to the bootstrap mode, the vector located at address $7FEE and $7FEF
(RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap
mode, the IRQ pin should be at 2xV_DD with the TCAP1 pin ‘high’ during transition of the RESET
pin from low to high. The hold time on the IRQ and TCAP1 pins is two clock cycles after the
external RESET pin is brought high.
When the MC68HC705B32 is placed in the bootstrap mode, the bootstrap reset vector will be
Preliminary ^{fetched and the bootstrap firmware will start to execute. Table H-4 shows the conditions required}
to enter each level of bootstrap mode on the rising edge of RESET.
Table H-4 Mode of operation selection
IRQ pin
V_SS to V_DD
2xV_DD
2xV_DD
2xV_DD
TCAP1 pin
V_SS to V_DD
V_DD
V_DD
V_DD
PD1 PD2 PD3 PD4
Mode
x x x x Single chip
0 0 0 x Erased EPROM verification
1
0
0
0
EPROM verification; erase EEPROM;
EPROM/EEPROM parallel program/verify
0
1
0
0
Erased EPROM verification;
no EEPROM erase if SEC is zero (parallel mode)
2xV_DD
V_DD
1
1
0
0
Erased EPROM verification; erase EEPROM;
EPROM parallel program/verify (no E²)
2xV_DD
V_DD
x 1 1 0 Jump to start of RAM ($0051); SEC bit = ACTIVE
Preliminary ^2xVDD
V_DD
2xV_DD
V_DD
x = Don’t care
0 1 0 1 EPROM and EEPROM verification; SEC bit = ACTIVE (parallel mode)
x
x
1
1
Serial RAM load/execute – similar to MC68HC05B6 but can fill RAM I,
II and III
The bootstrap program will first copy part of itself in RAM (except ‘RAM parallel load’), as the
program cannot be executed in ROM during verification/programming of the EPROM. It will then
set the TCMP1 output to a logic high level, unlike the MC68HC05B6 which keeps TCMP1 low. This
can be used to distinguish between the two circuits and, in particular, for selection of the VPP level
and current capability.
14
MC68HC05B6
Rev. 4.1
MC68HC705B32
Freescale
H-13