MC68HC05B6_13 Datasheet, PDF(110/302 Page) Freescale Semiconductor, Inc – Microcontrollers

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MC68HC05B6_13 Datasheet, PDF (110/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

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9.2

Interrupts

The MCU can be interrupted by four different sources: three maskable hardware interrupts and

one non maskable software interrupt:

â¢ External signal on the IRQ pin

â¢ Serial communications interface (SCI)

â¢ Programmable timer

â¢ Software interrupt instruction (SWI)

Interrupts cause the processor to save the register contents on the stack and to set the interrupt

mask (I-bit) to prevent additional interrupts. The RTI instruction (ReTurn from Interrupt) causes the

register contents to be recovered from the stack and normal processing to resume. While

executing the RTI instruction, the value of the I-bit is replaced by the corresponding I-bit stored on

the stack.

Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but

are considered pending until the current instruction is complete. The current instruction is the one

already fetched and being operated on. When the current instruction is complete, the processor

checks all pending hardware interrupts. If interrupts are not masked (I-bit clear) and the

corresponding interrupt enable bit is set, the processor proceeds with interrupt processing;

otherwise, the next instruction is fetched and executed.

Note: Power-on and external reset clear all interrupt enable bits, but set the INTE bit in the

miscellaneous register, thus preventing interrupts during the reset sequence.

9

9.2.1 Interrupt priorities

Each potential interrupt source is assigned a priority level, which means that if more than one

interrupt is pending at the same time, the processor will service the one with the highest priority

first. For example, if both an external interrupt and a timer interrupt are pending after an instruction

execution, the external interrupt is serviced first.

Table 9-2 shows the relative priority of all the possible interrupt sources. Figure 9-3 shows

the interrupt processing flow.

9.2.2 Nonmaskable software interrupt (SWI)

The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt: it is

executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI

is executed after interrupts that were pending when the SWI was fetched, but before interrupts

Freescale

9-6

RESETS AND INTERRUPTS

MC68HC05B6

Rev. 4.1

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