MC68HC05B6_13 Datasheet, PDF (106/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

9.1.1 Power-on reset
A power-on reset occurs when a positive transition is detected on VDD. The power-on reset
function is strictly for power turn-on conditions and should not be used to detect drops in the power
supply voltage. The power-on circuitry provides a stabilization delay (t_PORL) from when the
oscillator becomes active. If the external RESET pin is low at the end of this delay then the
processor remains in the reset state until RESET goes high. The user must ensure that the voltage
on VDD has risen to a point where the MCU can operate properly by the time t_PORL has elapsed.
If there is doubt, the external RESET pin should remain low until the voltage on VDD has reached
the specified minimum operating voltage. This may be accomplished by connecting an external
RC circuit to this pin to generate a power-on reset (POR). In this case, the time constant must be
great enough to allow the oscillator circuit to stabilize.
During power-on reset, the RESET pin is driven low during a t_PORL delay start-up sequence. t_PORL is
defined by a user specified mask option to be either 16 cycles or 4064 cycles (see Section 1.2).
A software distinction between a power-on reset and an external reset can be made using the
POR bit in the miscellaneous register (see Section 9.1.2).
9.1.2
Miscellaneous register
Miscellaneous
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000C POR⁽¹⁾ INTP INTN INTE SFA SFB SM WDOG⁽²⁾ ?001 000?
9
(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
POR — Power-on reset bit
This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the
user to make a software distinction between a power-on and an external reset. This bit cannot be
set by software and is cleared by writing it to zero.
1 (set) – A power-on reset has occurred.
0 (clear) – No power-on reset has occurred.
Note:
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
Freescale
9-2
RESETS AND INTERRUPTS
MC68HC05B6
Rev. 4.1