MC68HC05B6_13 Datasheet, PDF(166/302 Page) Freescale Semiconductor, Inc – Microcontrollers

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MC68HC05B6_13 Datasheet, PDF (166/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Table C-1 Register outline

Register name

Port A data (PORTA)

Port B data (PORTB)

Port C data (PORTC)

Port D data (PORTD)

Port A data direction (DDRA)

Port B data direction (DDRB)

Port C data direction (DDRC)

EPROM/ECLK control

A/D data (ADDATA)

A/D status/control (ADSTAT)

Pulse length modulation A (PLMA)

Pulse length modulation B (PLMB)

Miscellaneous

SCI baud rate (BAUD)

SCI control 1 (SCCR1)

SCI control 2 (SCCR2)

SCI status (SCSR)

SCI data (SCDR)

Timer control (TCR)

Timer status (TSR)

Input capture high 1

Input capture low 1

Output compare high 1

Output compare low 1

Timer counter high

Timer counter low

Alternate counter high

Alternate counter low

Input capture high 2

Input capture low 2

Output compare high 2

Output compare low 2

Options (OPTR)(4)

Address bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State on

reset

$0000

Undefined

$0001

Undefined

$0002

PC2/

ECLK

Undefined

$0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined

$0004

0000 0000

$0005

0000 0000

$0006

$0007

EPPT(1) ELAT EPGM ECLK

0000 0000

u?00 0uuu

$0008

0000 0000

$0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

$000A

0000 0000

$000B

0000 0000

$000C POR(2) INTP INTN INTE SFA SFB SM WDOG(3) ?001 000?

$000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

$000E R8 T8

M WAKE CPOL CPHA LBCL uuuu

$000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

$0010 TDRE TC RDRF IDLE OR NF FE

1100 000u

$0011

0000 0000

$0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

$0013 ICF1 OCF1 TOF ICF2 OCF2

uuuu

$0014

Undefined

$0015

Undefined

$0016

Undefined

$0017

Undefined

$0018

1111 1111

$0019

1111 1100

$001A

1111 1111

$001B

1111 1100

$001C

Undefined

$001D

Undefined

$001E

Undefined

$001F

Undefined

$1EFE

EPP 0 RTIM RWAT WWAT PBPD PCPD Not affected

(1) This bit reflects the state of the EPP bit in the options register ($1EFE) at reset.

(2) This bit is set each time the device is powered-on.

(3) The state of the WDOG bit after reset depends on the mask option selected; â1â = watchdog enabled and â0â = watchdog disabled.

(4) Because this register is implemented in EPROM, reset has no effect on the state of the individual bits.

14

Freescale

C-4

MC68HC705B5

MC68HC05B6

Rev. 4.1

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