MC68HC05B6_13 Datasheet, PDF (46/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

E1LAT — EEPROM programming latch enable bit
1 (set) – Address and data can be latched into the EEPROM for further
program or erase operations, providing the E1PGM bit is cleared.
0 (clear) – Data can be read from the EEPROM. The E1ERA bit and the E1PGM
3
bit are reset to zero when E1LAT is ‘0’.
STOP, power-on and external reset clear the E1LAT bit.
Note:
After the t_ERA1 erase time or t_PROG1 programming time, the E1LAT bit has to be reset
to zero in order to clear the E1ERA bit and the E1PGM bit.
E1PGM — EEPROM charge pump enable/disable
1 (set) – Internal charge pump generator switched on.
0 (clear) – Internal charge pump generator switched off.
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array.
This bit cannot be set before the data is selected, and once this bit has been set it can only be
cleared by clearing the E1LAT bit.
A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are give in Table 3-1.
Table 3-1 EEPROM control bits description
E1ERA
0
0
0
1
1
E1LAT
0
1
1
1
1
E1PGM
Description
0 Read condition
0 Ready to load address/data for program/erase
1 Byte programming in progress
0 Ready for byte erase (load address)
1 Byte erase in progress
Note:
All combinations are not shown in the above table, since the E1PGM and E1ERA bits
are cleared when the E1LAT bit is at zero, and will result in a read condition.
Freescale
3-4
MEMORY AND REGISTERS
MC68HC05B6
Rev. 4.1