MC68HC05B6_13 Datasheet, PDF (275/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

Preliminary ^{Table H-8 DC electrical characteristics for 3.3V operation}
(V_DD = 3.3Vdc ± 10%, V_SS = 0Vdc, T_A = –40 to +85°C)
Characteristic⁽¹⁾
Symbol
Min
Typ⁽²⁾
Max
Output voltage
I_LOAD = – 10 µA
I_LOAD = +10 µA
Output high voltage (I_LOAD = 0.8mA)
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2
Output high voltage (I_LOAD = 1.6mA)
TDO, SCLK, PLMA, PLMB
OutpuPtAlo0w–7v,oPltBa0g–e7(,I_{LPOCA0D–=7,1T.6CmMAP)1, TCMP2,}
TDO, SCLK, PLMA, PLMB
Output low voltage
RESET
(I_LOAD
=
1.6
mA)
V_OH
V_DD – 0.1
—
—
V_OL
—
—
0.1
V_OH
V_DD – 0.3 V_DD – 0.1
—
V_OH
V_DD – 0.3 V_DD – 0.1
—
V_OL
—
0.1
0.3
V_OL
0.2
0.6
Unit
V
V
V
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
V_IH
0.7V_DD
—
V_DD
V
Preliminary ^{Input low voltage}
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,
V_IL
RESET, TCAP1, TCAP2, RDI
Supply current⁽³⁾ (For Guidance Only)
RUN (SM = 0) (See Figure 11-1)
I_DD
RUN (SM = 1) (See Figure 11-2)
I_DD
WAIT (SM = 0) (See Figure 11-3)
WAIT (SM = 1) (See Figure 11-4)
II_DDDD
STOP
0 to 70 (standard)
I_DD
– 40 to 85 (extended)
I_DD
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK I_IL
Input current (0 to 70)
IRQ, OSC1, TCAP1, TCAP2, RDI,
I_IN
V_SS
—
0.2V_DD
—
3
TBD
—
1
TBD
—
1.5
TBD
—
0.5
TBD
—
10
TBD
—
10
TBD
—
±0.2
±1
—
±0.2
±1
V
mA
mA
mA
mA
µA
µA
µA
µA
PD0/AN0-PD7/AN7 (channel not selected)
Input current (– 40 to 125)
IRQ, OSC1, TCAP1, TCAP2, RDI,
I_IN
—
—
±5
µA
PD0/AN0-PD7/AN7 (channel not selected)
Preliminary ^Capacitance
Ports (as input or output), RESET, TDO,
SCLK
IRQ, TCAP1, TCAP2, OSC1, RDI
PD0/AN0–PD7/AN7 (A/D off)
PD0/AN0–PD7/AN7 (A/D on)
C_OUT
CC_OIUNT
C_IN
—
—
—
—
—
12
pF
—
8
pF
12
—
pF
22
—
pF
(1) All I_DD measurements taken with suitable decoupling capacitors across the power supply to suppress the
transient switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3)
RUN
0.2 V
afrnodmWraAiIl;TnIo_{DDD:Cmleoaasdusr;emd auxsiimngumanloeaxdteornnaol ustqpuuatsre5-0wpaFve(2c0lopcFkosnouOrSceC2(f)O. SC}
=
2.0
MHz);
all
inputs
STOP /WAIT I_DD: all ports configured as inputs; V_IL = 0.2 V and V_IH = V_DD – 0.2 V: STOP I_DD measured with
OSC1 = V_DD.
WAIT I_DD is affected linearly by the OSC2 capacitance.
14
MC68HC05B6
Rev. 4.1
MC68HC705B32
Freescale
H-25