MC68HC05B6_13 Datasheet, PDF (104/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

8.3
A/D converter during STOP mode
When the MCU enters STOP mode with the A/D converter turned on, the A/D clocks are stopped
and the A/D converter is disabled for the duration of STOP mode, including the 4064 cycles
start-up time. If the A/D RC oscillator is in operation it will also be disabled.
8.4
A/D converter during WAIT mode
The A/D converter is not affected by WAIT mode and continues normal operation.
In order to reduce power consumption the A/D converter can be disconnected, under software
control using the ADON bit and the ADRC bit in the A/D status/control register at $0009, before
entering WAIT mode.
8.5
Port D analog input
The external analog voltage value to be processed by the A/D converter is sampled on an internal
capacitor through a resistive path, provided by input-selection switches and a sampling aperture
8
time switch, as shown in Figure 8-2. Sampling time is limited to 12 bus clock cycles. After
sampling, the analog value is stored on the capacitor and held until the end of conversion. During
this hold time, the analog input is disconnected from the internal A/D system and the external
voltage source sees a high impedance input.
The equivalent analog input during sampling is an RC low-pass filter with a minimum resistance
of 50 kΩ and a capacitance of at least 10pF. It should be noted that these are typical values
measured at room temperature.
Analog
input
pin
Input protection device
≥ 50kΩ
< 2pF
+ ∼20V
- ∼0.7V
1 µA
junction
leakage
≥ 10pF
DAC
capacitance
V_RL
Note:
The analog switch is closed during the 12 cycle sample time only.
Figure 8-2 Electrical model of an A/D input pin
Freescale
8-6
ANALOG TO DIGITAL CONVERTER
MC68HC05B6
Rev. 4.1