MC68HC05B6_13 Datasheet, PDF (107/302 Pages) Freescale Semiconductor, Inc – Microcontrollers

9.1.3 RESET pin
When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied
to the RESET input for a minimum period of 1.5 machine cycles (t_CYC). An internal Schmitt Trigger
is used to improve noise immunity on this pin. When the RESET pin goes high, the MCU will
resume operation on the following cycle. When a reset condition occurs internally, i.e. from POR
or the COP watchdog, the RESET pin provides an active-low open drain output signal which may
be used to reset external hardware. Current limitation to protect the pull-down device is provided
in case an RC type external reset circuit is used.
9.1.4 Computer operating properly (COP) watchdog reset
The watchdog counter system consists of a divide-by-8 counter, preceded by a fixed divide-by-4
and a fixed divide-by-256 prescaler, plus control logic as shown in Figure 9-2. The divide-by-8
counter can be reset by software.
Main CPU
clock
S
R
Latch
f_OSC/2
f_OSC/32
÷4
prescaler
÷ 256
(Bit 7 of free
running counter)
÷ 8 watchdog
counter
Power-on
Reset
pin
9
WDOG bit
Control logic
Schmitt
trigger
Input
protection
Figure 9-2 Watchdog system block diagram
Warning: The input to the watchdog system is derived from the carry output of bit 7 of the free
running timer counter. Therefore, a reset of the timer may affect the period of the
watchdog timeout.
The watchdog system can be automatically enabled, following power-on or external reset, via a
mask option (see Section 1.2), or it can be enabled by software by writing a ‘1’ to the WDOG bit
in the miscellaneous register at $000C (see Section 9.1.2). Once enabled, the watchdog system
MC68HC05B6
Rev. 4.1
RESETS AND INTERRUPTS
Freescale
9-3