MC9S12E256 Datasheet, PDF (89/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
Register
Name
RESERVED2
RESERVED3
RESERVED4
Bit 7
6
5
4
3
2
R
0
0
0
0
0
0
W
R
0
0
0
0
0
0
W
R
0
0
0
0
0
0
W
= Unimplemented or Reserved
Figure 2-3. FTS256K2 Register Summary (continued)
1
Bit 0
0
0
0
0
0
0
2.3.2.1 Flash Clock Divider Register (FCLKDIV)
The unbanked FCLKDIV register is used to control timed events in program and erase algorithms.
R
W
Reset
7
FDIVLD
0
6
5
4
3
2
PRDIV8
FDIV5
FDIV4
FDIV3
FDIV2
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-4. Flash Clock Divider Register (FCLKDIV)
1
FDIV1
0
0
FDIV0
0
All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.
Table 2-4. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
6
PRDIV8
Clock Divider Loaded.
0 Register has not been written.
1 Register has been written to since the last reset.
Enable Prescalar by 8.
0 The oscillator clock is directly fed into the clock divider.
1 The oscillator clock is divided by 8 before feeding into the clock divider.
5-0
FDIV[5:0]
Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz–200 kHz. The maximum divide ratio is 512. Please refer to Section 2.4.1.1, “Writing the
FCLKDIV Register” for more information.
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
89