MC9S12E256 Datasheet, PDF (136/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 3 Port Integration Module (PIM9E256V1)
3.3.2 Port M
Port M is associated with the serial communication interface (SCI2) , Inter-IC bus (IIC) and the digital to
analog converter (DAC0 and DAC1) modules. Each pin is assigned to these modules according to the
following priority: IIC/SCI2/DAC1/DAC0 > general-purpose I/O.
When the IIC bus is enabled, the PM[7:6] pins become SCL and SDA respectively. Refer to Chapter 10,
“Inter-Integrated Circuit (IICV2)” for information on enabling and disabling the IIC bus.
When the SCI2 receiver and transmitter are enabled, the PM[5:4] become RXD2 and TXD2 respectively.
Refer to Chapter 8, “Serial Communication Interface (SCIV4)” for information on enabling and disabling
the SCI receiver and transmitter.
When the DAC1 and DAC0 outputs are enabled, the PM[1:0] become DAO1 and DAO0 respectively.
Refer to Chapter 7, “Digital-to-Analog Converter (DAC8B1CV1)” for information on enabling and
disabling the DAC output.
During reset, PM[3] and PM[1:0] pins are configured as high-impedance inputs and PM[7:4] pins are
configured as pull-up inputs.
3.3.2.1 Port M I/O Register (PTM)
7
6
5
4
3
2
1
0
R
0
PTM7
W
PTM6
PTM5
PTM4
PTM3
PTM1
PTM0
IIC: SCL
SDA
SCI2:
TXD2
RXD2
DAC1/DAC0:
DAO1
DAO0
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 3-10. Port M I/O Register (PTM)
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRMx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRMx) is set to 0 (input), a read returns the value of the pin.
MC9S12E256 Data Sheet, Rev. 1.08
136
Freescale Semiconductor