MC9S12E256 Datasheet, PDF (332/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
11.3.2.7 PMF Fault Status Register (PMFFSTA)
Module Base + 0x0006
7
6
5
4
3
2
1
0
R
0
0
0
0
FFLAG3
FFLAG2
FFLAG1
FFLAG0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-10. PMF Fault Flag Register (PMFFSTA)
Read and write anytime.
Table 11-8. PMFFSTA Field Descriptions
Field
Description
6, 4, 2, 0
FFLAG[3:0]
Fault x Pin Flag — This flag is set after the required number of samples have been detected after a rising edge
on the FAULTx pin. Writing a logic one to FFLAGx clears it. Writing a logic zero has no effect. The fault protection
is enabled when FPINEx is set even when the PWMs are not enabled; therefore, a fault will be latched in,
requiring to be cleared in order to prevent an interrupt.
0 No fault on the FAULTx pin.
1 Fault on the FAULTx pin.
Note: Clearing FFLAGx satisfies pending FFLAGx CPU interrupt requests.
where x is 0, 1, 2 and 3.
11.3.2.8 PMF Fault Qualifying Samples Register (PMFQSMP)
Module Base + 0x0007
R
W
Reset
7
6
QSMP3
5
4
QSMP2
3
2
QSMP1
1
0
QSMP0
0
0
0
0
0
0
0
0
Figure 11-11. PMF Fault Qualifying Samples Register (PMFQSMP)
Read anytime. This register cannot be modified after the WP bit is set.
Table 11-9. PMFQSMP Field Descriptions
Field
Description
7–0
QSMP[3:0]
Fault x Qualifying Samples — This field indicates the number of consecutive samples taken at the FAULTx pin
to determine if a fault is detected. The first sample is qualified after two bus cycles from the time the fault is
present and each sample after that is taken every four bus cycles. See Table 11-10.
where x is 0, 1, 2 and 3.
MC9S12E256 Data Sheet, Rev. 1.08
332
Freescale Semiconductor