MC9S12E256 Datasheet, PDF (74/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1)
an external program (again through BDM commands). Note that if the part goes through a reset before the
security bits are reprogrammed to the unsecure state, the part will be secured again.
1.8 Low Power Modes
The microcontroller features three main low power modes. Consult the respective block description
chapter for information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source
of information about the clock system is Chapter 4, “Clocks and Reset Generator (CRGV4)”.
1.8.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.
1.8.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.
1.8.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and data bus) will be fully static. All peripherals stay
active. For further power consumption the peripherals can individually turn off their local clocks.
1.8.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.
1.9 Resets and Interrupts
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts. System resets can be generated through external control of the RESET pin, through the clock
and reset generator module CRG or through the low voltage reset (LVR) generator of the voltage regulator
module. Refer to Chapter 4, “Clocks and Reset Generator (CRGV4)” and Chapter 14, “Dual Output
Voltage Regulator (VREG3V3V2)” for detailed information on reset generation.
1.9.1 Vectors
Table 1-9 lists interrupt sources and vectors in default order of priority.
MC9S12E256 Data Sheet, Rev. 1.08
74
Freescale Semiconductor