MC9S12E256 Datasheet, PDF (545/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 19 Module Mapping Control (MMCV4)
19.3.2.1 Initialization of Internal RAM Position Register (INITRM)
7
6
5
4
3
2
1
R
0
0
RAM15
RAM14
RAM13
RAM12
RAM11
W
Reset
0
0
0
0
1
0
0
= Unimplemented or Reserved
Read: Anytime
Figure 19-3. Initialization of Internal RAM Position Register (INITRM)
Write: Once in normal and emulation modes, anytime in special modes
NOTE
Writes to this register take one cycle to go into effect.
0
RAMHAL
1
This register initializes the position of the internal RAM within the on-chip system memory map.
Table 19-2. INITRM Field Descriptions
Field
Description
7:3
Internal RAM Map Position — These bits determine the upper five bits of the base address for the system’s
RAM[15:11] internal RAM array.
0
RAMHAL
RAM High-Align — RAMHAL specifies the alignment of the internal RAM array.
0 Aligns the RAM to the lowest address (0x0000) of the mappable space
1 Aligns the RAM to the higher address (0xFFFF) of the mappable space
19.3.2.2 Initialization of Internal Registers Position Register (INITRG)
7
6
5
4
3
2
1
0
R
0
0
0
0
REG14
REG13
REG12
REG11
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-4. Initialization of Internal Registers Position Register (INITRG)
Read: Anytime
Write: Once in normal and emulation modes and anytime in special modes
This register initializes the position of the internal registers within the on-chip system memory map. The
registers occupy either a 1K byte or 2K byte space and can be mapped to any 2K byte space within the first
32K bytes of the system’s address space.
Table 19-3. INITRG Field Descriptions
Field
Description
6:3
Internal Register Map Position — These four bits in combination with the leading zero supplied by bit 7 of
REG[14:11] INITRG determine the upper five bits of the base address for the system’s internal registers (i.e., the minimum
base address is 0x0000 and the maximum is 0x7FFF).
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
545