MC9S12E256 Datasheet, PDF (154/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 3 Port Integration Module (PIM9E256V1)
3.3.7 Port U
Port U is associated with one 4-channel timer (TIM2) and the pulse width modulator (PWM) module. Each
pin is assigned to these modules according to the following priority: TIM2/PWM > general-purpose I/O.
If the timer TIM2 is enabled, the channels configured for output compare are available on port U pins
PU[3:0]. Refer to Chapter 13, “Timer Module (TIM16B4CV1)” for information on enabling and disabling
the TIM module.
When a PWM channel is enabled, the corresponding pin becomes a PWM output. Refer to Chapter 3, “Port
Integration Module (PIM9E256V1)” for information on enabling and disabling the PWM channels.
If both PWM and TIM2 are enabled simultaneously, the pin functionality is determined by the
configuration of the MODRR bits
During reset, port U pins are configured as high-impedance inputs.
3.3.7.1 Port U I/O Register (PTU)
R
W
PWM:
7
PTU7
6
PTU6
5
PTU5
PW15
4
PTU4
PW14
3
PTU3
PW13
2
PTU2
PW12
1
PTU1
PW11
0
PTU0
PW10
TIM2:
OC27
OC26
OC25
OC24
Reset
0
0
0
0
0
0
0
0
Figure 3-42. Port U I/O Register (PTU)
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRUx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRUx) is set to 0 (input), a read returns the value of the pin.
3.3.7.2 Port U Input Register (PTIU)
7
R PTIU7
W
6
PTIU6
5
PTIU5
4
PTIU4
3
PTIU3
2
PTIU2
Reset
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 3-43. Port U Input Register (PTIU)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
1
PTIU1
u
0
PTIU0
u
MC9S12E256 Data Sheet, Rev. 1.08
154
Freescale Semiconductor