MC9S12E256 Datasheet, PDF (551/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 19 Module Mapping Control (MMCV4)
Table 19-11. Allocated FLASH/ROM Physical Memory Space
rom_sw1:rom_sw0
Allocated FLASH
or ROM Space
00
0K byte
01
16K bytes
10
48K bytes⁽¹⁾
11
64K bytes⁽¹⁾
NOTES:
1. The ROMHM software bit in the MISC register determines the accessibility of the
FLASH/ROM memory space. Please refer to Section 19.3.2.8, “Memory Size Register
1 (MEMSIZ1),” for a detailed functional description of the ROMHM bit.
Table 19-12. Allocated Off-Chip Memory Options
pag_sw1:pag_sw0
00
01
10
11
Off-Chip Space
876K bytes
768K bytes
512K bytes
0K byte
On-Chip Space
128K bytes
256K bytes
512K bytes
1M byte
NOTE
As stated, the bits in this register provide read visibility to the system
memory space and on-chip/off-chip partitioning allocations defined at
system integration. The actual array size for any given type of memory
block may differ from the allocated size. Please refer to Chapter 1,
“MC9S12E256 Device Overview (MC9S12E256DGV1)” for actual sizes.
19.3.2.9 Program Page Index Register (PPAGE)
7
R
0
W
Reset¹
—
6
5
4
3
2
1
0
0
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
—
—
—
—
—
—
—
1. The reset state of this register is controlled at chip integration. Please refer to Chapter 1, “MC9S12E256 Device Overview
(MC9S12E256DGV1)” to determine the actual reset state of this register.
= Unimplemented or Reserved
Read: Anytime
Figure 19-11. Program Page Index Register (PPAGE)
Write: Determined at chip integration. Generally it’s: “write anytime in all modes;” on some devices it will
be: “write only in special modes.” Check specific device documentation to determine which applies.
Reset: Defined at chip integration as either 0x00 (paired with write in any mode) or 0x3C (paired with
write only in special modes), see Chapter 1, “MC9S12E256 Device Overview (MC9S12E256DGV1)”.
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
551