MC9S12E256 Datasheet, PDF (350/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
Table 11-40. PMFFQCC Field Descriptions (continued)
Field
Description
2
PRSCC
Prescaler C — This buffered field selects the PWM clock frequency illustrated in Table 11-42.
Note: Reading the PRSCC field reads the buffered value and not necessarily the value currently in effect. The
PRSCC field takes effect at the beginning of the next PWM cycle and only when the load okay bit, LDOKC,
is set.
0
PWMRFC
PWM Reload Flag C — This flag is set at the beginning of every reload cycle regardless of the state of the
LDOKC bit. Clear PWMRFC by reading PMFFQCC with PWMRFC set and then writing a logic one to the
PWMRFC bit. If another reload occurs before the clearing sequence is complete, writing logic one to PWMRFC
has no effect.
0 No new reload cycle since last PWMRFC clearing
1 New reload cycle since last PWMRFC clearing
Note: Clearing PWMRFC satisfies pending PWMRFC CPU interrupt requests.
LDFQC
0000
0001
0010
0011
0100
0101
0110
0111
Table 11-41. PWM Reload Frequency C
PWM Reload Frequency
Every PWM opportunity
Every 2 PWM opportunities
Every 3 PWM opportunities
Every 4 PWM opportunities
Every 5 PWM opportunities
Every 6 PWM opportunities
Every 7 PWM opportunities
Every 8 PWM opportunities
LDFQ[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
PWM Reload Frequency
Every 9 PWM opportunities
Every 10 PWM opportunities
Every 11 PWM opportunities
Every 12 PWM opportunities
Every 13 PWM opportunities
Every 14 PWM opportunities
Every 15 PWM opportunities
Every 16 PWM opportunities
Table 11-42. PWM Prescaler C
PRSCC
00
01
10
11
PWM Clock Frequency
f_bus
f_bus/2
f_bus/4
f_bus/8
MC9S12E256 Data Sheet, Rev. 1.08
350
Freescale Semiconductor