MC9S12E256 Datasheet, PDF (353/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

11.4 Functional Description
Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
11.4.1 Block Diagram
A block diagram of the PMF is shown in Figure 11-1. The MTG bit allows the use of multiple PWM
generators (A, B, and C) or just a single generator (A). PWM0 and PWM1 constitute Pair A, PWM2 and
PWM3 constitute Pair B, and PWM4 and PWM5 constitute Pair C.
11.4.2 Prescaler
To permit lower PWM frequencies, the prescaler produces the PWM clock frequency by dividing the bus
clock frequency by one, two, four, and eight. Each PWM generator has its own prescaler divisor. Each
prescaler is buffered and will not be used by its PWM generator until the corresponding Load OK bit is set
and a new PWM reload cycle begins.
11.4.3 PWM Generator
Each PWM generator contains a 15-bit up/down PWM counter producing output signals with
software-selectables:
• Alignment—The logic state of each pair EDGE bit determines whether the PWM pair outputs are
edge-aligned or center-aligned
• Period—The value written to each pair PWM counter modulo register is used to determine the
PWM pair period. The period can also be varied by using the prescaler
— With edge-aligned output, the modulus is the period of the PWM output in clock cycles
— With center-aligned output, the modulus is one-half of the PWM output period in clock cycles
• Pulse width—The number written to the PWM value register determines the pulse width duty cycle
of the PWM output in clock cycles
— With center-aligned output, the pulse width is twice the value written to the PWM value register
— With edge-aligned output, the pulse width is the value written to the PWM value register
11.4.3.1 Alignment
Each edge-align bit, EDGEx, selects either center-aligned or edge-aligned PWM generator outputs.
ALIGNMENT REFERENCE
UP/DOWN COUNTER
MODULUS = 4
PWM OUTPUT
DUTY CYCLE = 50%
Figure 11-41. Center-Aligned PWM Output
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
353