MC9S12E256 Datasheet, PDF (244/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 8 Serial Communication Interface (SCIV4)
• Programmable transmitter output parity
• Two receiver wakeup methods:
— Idle line wakeup
— Address mark wakeup
• Interrupt-driven operation with eight flags:
— Transmitter empty
— Transmission complete
— Receiver full
— Idle receiver input
— Receiver overrun
— Noise error
— Framing error
— Parity error
• Receiver framing error detection
• Hardware parity checking
• 1/16 bit-time noise detection
8.1.3 Modes of Operation
The SCI functions the same in normal, special, and emulation modes. It has two low-power modes, wait
and stop modes.
8.1.3.1 Run Mode
Normal mode of operation.
8.1.3.2 Wait Mode
SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1
(SCICR1).
• If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode.
• If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation
state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver
enable bit, RE, or the transmitter enable bit, TE.
If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The
transmission or reception resumes when either an internal or external interrupt brings the CPU out
of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and
resets the SCI.
MC9S12E256 Data Sheet, Rev. 1.08
244
Freescale Semiconductor