MC9S12E256 Datasheet, PDF (298/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 10 Inter-Integrated Circuit (IICV2)
10.1.3 Block Diagram
The block diagram of the IIC module is shown in Figure 10-1.
IIC
Registers
Interrupt
bus_clock
Clock
Control
Start
Stop
Arbitration
Control
In/Out
Data
Shift
Register
SCL
SDA
Address
Compare
Figure 10-1. IIC Block Diagram
10.2 External Signal Description
The IICV2 module has two external pins.
10.2.1 IIC_SCL — Serial Clock Line Pin
This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification.
10.2.2 IIC_SDA — Serial Data Line Pin
This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification.
10.3 Memory Map and Register Definition
This section provides a detailed description of all memory and registers for the IIC module.
10.3.1 Module Memory Map
The memory map for the IIC module is given below in Figure 10-2. The address listed for each register is
the address offset.The total address for each register is the sum of the base address for the IIC module and
the address offset for each register.
MC9S12E256 Data Sheet, Rev. 1.08
298
Freescale Semiconductor