MC9S12E256 Datasheet, PDF (349/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
Table 11-39. PMFENCC Field Descriptions (continued)
Field
Description
1
LDOKC
Load Okay C — If MTG is clear, this bit reads zero and can not be written.
If MTG is set, this bit loads the PRSCC bits, the PMFMODC register and the PWMVAL4–5 registers into a set of
buffers. The buffered prescaler divisor C, PWM counter modulus C value, PWM4–5 pulse widths take effect at
the next PWM reload.
Set LDOKC by reading it when it is logic zero and then writing a logic one to it. LDOKC is automatically cleared
after the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Reset
clears LDOKC.
0 Do not load new modulus C, prescaler C, and PWM4–5 values.
1 Load prescaler C, modulus C, and PWM4–5 values.
Note: Do not set PWMENC bit before setting the LDOKC bit and do not clear the LDOKC bit at the same time
as setting the PWMENC bit.
0
PWMRIEC
PWM Reload Interrupt Enable C — If MTG is clear, this bit reads zero and cannot be written.
If MTG is set, this bit enables the PWMRFC flag to generate CPU interrupt requests.
0 PWMRFC CPU interrupt requests disabled
1 PWMRFC CPU interrupt requests enabled
11.3.2.31 PMF Frequency Control C Register (PMFFQCC)
Module Base + 0x0031
7
R
W
Reset
0
6
5
LDFQC
4
3
2
1
HALFC
PRSCC
0
0
0
0
0
0
Figure 11-37. PMF Frequency Control C Register (PMFFQCC)
0
PWMRFC
0
Read anytime and write only if MTG is set.
Table 11-40. PMFFQCC Field Descriptions
Field
7–4
LDFQC
3
HALFC
Description
Load Frequency C — This field selects the PWM load frequency according to Table 11-41. See
Section 11.4.7.2, “Load Frequency” for more details.
Note: The LDFQC field takes effect when the current load cycle is complete, regardless of the state of the load
okay bit, LDOKC. Reading the LDFQC field reads the buffered value and not necessarily the value
currently in effect.
Half Cycle Reload C — This bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect
on edge-aligned PWMs.
0 Half-cycle reloads disabled
1 Half-cycle reloads enabled
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
349